1. Field of the Invention
The present invention generally relates to a semiconductor device and, more specifically, to a bonding pad electrode structure which is improved to have sufficiently large allowance current and to prevent generation of cracks in an interlayer insulating film derived from mechanical stress at the time of wire bonding.
2. Description of the Background Art
FIG. 8 is a plan view of a conventional wafer. On a wafer 10, a plurality of chips 11 are formed. On the chip 11, a semiconductor device is formed (not shown).
FIG. 9 is an enlarged view of the chip 11. A circuit (I/O buffer circuit or input protecting circuit) 12 is provided on chip 11. Bonding pads 13 are formed on chip 11.
Referring to FIG. 10, chip 11 is mounted on a metal frame 14, bonded to a lead 17 by means of a wire 15, and then sealed by a resin 16. Wire 15 connects bonding pad 13 and lead 17. FIG. 11 is an enlarged view of the terminal on the chip, that is, the portion of the bonding pad. Bonding pad 13 is classified into a wire bonding area 18 and a drawing line area 19. At drawing line area 19, a drawing line for connecting wire bonding region 18 with the circuit 12 is placed.
FIG. 12 is a cross section of a conventional bonding pad electrode structure. FIG. 12 is a cross section taken along the line XII--XII of FIG. 11.
Referring to FIG. 12, the bonding pad includes a first interlayer insulating film 2a provided on a silicon substrate 1. On first interlayer insulating film 2a, a lower interconnection layer 3 is provided. On the first interlayer insulating film 2a, a second interlayer insulating film 2b is provided to cover lower interconnection layer 3. In the second interlayer insulating film 2b, a via hole 5 is provided for exposing a portion of a surface of the lower interconnection layer 3. An uppermost interconnection layer 4 is provided on the second interlayer insulating film 2b to be in contact with lower interconnection layer 3 through via hole 5. The surface of the uppermost interconnection layer 4 is used as a bonding pad, to which wire 15 is bonded.
The electrode structure of the bonding pad shown in FIG. 12 suffers from the following problem.
Namely, if the diameter of via hole 5 is made about 0.8 .mu.m or smaller, a technique for filling a conductive material in the via hole 5 and forming upper interconnection layer 4 thereon becomes necessary. According to this technique, it is necessary to deposit a conductive material, for example tungsten, on silicon substrate 1 so as to fill contact hole 5 by the CVD method. It is also necessary to etch back the deposited tungsten by dry etching thereafter, so as to leave tungsten only in the via hole. However, this is difficult in such a large via hole 5 as shown in FIG. 12 for the following reasons.
More specifically, referring to FIG. 13, a conductive material, for example, tungsten film 21, is deposited on silicon substrate 1 by the CVD method. Then, when tungsten film 21 is etched back by dry etching as shown in FIG. 14, the via hole 5 which is large, cannot be filled with tungsten but the tungsten film 21 is left only as etching residue on sidewalls of the via hole 5. Such residue of etching would be foreign matter when peeled off, which has significant influence on production yield. This is the problem encountered when the electrode structure of the bonding pad shown in FIG. 12 is employed.
FIG. 15 is a cross section of a conventional bonding pad electrode structure, manufactured using a technique of filling conductive material.
Referring to FIG. 15, the bonding pad portion includes a first interlayer insulating film 2a formed on silicon substrate 1. On the first interlayer insulating film 2a, a lower interconnection layer 3 is provided. A second interlayer insulating film 2b is provided on the first interlayer insulating film 2a to cover lower interconnection layer 3. On the second interlayer insulating film 2b, an uppermost interconnection layer 4 is provided. In the second interlayer insulating film 2b, a via hole 6 having an appropriate size to be filled with a conductive material is provided, connecting the uppermost interconnection layer 4 and the lower interconnection layer 3. In via hole 6, a conductive material 6a for electrically connecting the uppermost interconnection layer 4 and the lower interconnection layer 3 is filled. The uppermost interconnection layer 4 is used as a bonding pad, to which wire 15 is bonded.
The electrode structure of the bonding pad is formed to have multilayered interconnections for the following reasons.
Namely, when amount of current per one electrode increases, the interconnection would be disconnected by electromigration if the interconnection includes only one layer. In order to prevent disconnection, it is necessary to disperse current to a number of layers of a multi-layered interconnection. For this reason, it is necessary to provide connection between the multi-layered interconnection somewhere at the electrode. Conventionally, connection between the multi-layered interconnection has been provided at the wire bonding area.
As described above, in the conventional bonding pad electrode structure cannot satisfy the technique for filling the via hole. In the electrode structure of the bonding pad shown in FIG. 16, cracks 22 may be generated at a portion sandwiched between the uppermost interconnection layer and the lower interconnection layer of the interlayer insulating film 2b during wire bonding as shown in FIG. 16, and therefore reliability cannot be ensured.